The PCB impedance calculator above implements the closed-form microstrip and stripline equations published in IPC-2141, the design guide for controlled impedance circuit boards issued by IPC, now trading as the Global Electronics Association. Those equations are the ones printed in most signal integrity textbooks and built into most quick estimators, and they are useful for exactly what they were meant for: choosing a starting geometry and understanding which variable moves the answer.
Arb Digital publishes free engineering calculators that name the model they implement and state where it stops being trustworthy. So it is worth saying at the top: a formula does not confirm a controlled-impedance board. The stack-up your fabricator actually builds and a time-domain reflectometry measurement on a coupon from your own panel are what confirm it. Treat this page as the tool for the first conversation with your fabricator, not the last.
What This PCB Impedance Calculator Does
Characteristic impedance is the ratio of voltage to current in a wave travelling along a transmission line, and for a lossless line it equals the square root of inductance per unit length divided by capacitance per unit length. On a printed board both of those are set by geometry and by the dielectric surrounding the copper, so impedance falls out of four numbers: trace width, copper thickness, distance to the reference plane and the dielectric constant.
The calculator returns the single-ended characteristic impedance as the headline figure. The grid adds propagation delay in picoseconds per inch, the effective permittivity the wave actually experiences, the width-to-height ratio that determines whether the equations are inside their validity window, and an estimated differential impedance for a coupled pair at the spacing you entered.
This page is about the impedance of a trace. It is a different question from how wide a trace must be to carry a given current without overheating, which is a thermal problem governed by IPC-2221 and handled by the PCB trace width calculator. Those two pages regularly give conflicting widths for the same trace, and when they do, the answer is that both constraints apply and the trace must satisfy the harder one.
How to Use It
- Get the dielectric height from a real stack-up. For microstrip it is the prepreg or core thickness between the trace and the first solid plane, not the total board thickness. If a plane was reassigned to signals mid-project, the height can double without anyone updating the impedance target.
- Use the finished copper thickness. Outer layers are plated after etching, so a half-ounce starting foil can finish closer to one ounce. Inner layers do not plate and stay near their nominal thickness.
- Use the laminate's dielectric constant at your frequency. FR-4 is a family, not a number. A datasheet value at 1 GHz can differ noticeably from the same material at 100 MHz, and glass weave adds direction dependence on top of that.
- Check the width-to-height ratio the calculator reports. The IPC-2141 microstrip equation is fitted for a ratio between about 0.1 and 3.0, and it degrades outside that window.
- Send the geometry to your fabricator, not the impedance. Specify the target impedance and the tolerance, and let them adjust widths for their process. A fabricator's own field solver models their plating, etch profile and resin content in a way no closed-form equation can.
The Formulas and a Worked Example
The IPC-2141 microstrip relation is Z₀ = 87 ÷ √(εr + 1.41) × ln(5.98h ÷ (0.8w + t)). The stripline relation is Z₀ = 60 ÷ √εr × ln(4b ÷ (0.67π(0.8w + t))), where b is the plane-to-plane separation. Both are empirical fits to field-solver results, which is why they contain unexplained constants like 5.98 and 1.41 rather than being derivable.
Work the microstrip default through by hand. With w = 0.25 mm, t = 0.035 mm, h = 0.15 mm and εr = 4.2: the denominator term is 0.8 × 0.25 + 0.035 = 0.235 mm, and 5.98 × 0.15 = 0.897 mm, so the logarithm is ln(3.817) = 1.3396. The prefactor is 87 ÷ √5.61 = 87 ÷ 2.3685 = 36.73. Multiplying gives Z₀ = 49.2 Ω, which is why that geometry is a common starting point for a 50-ohm microstrip on a thin outer dielectric.
Effective permittivity for microstrip uses the companion approximation εeff = 0.475εr + 0.67, giving 0.475 × 4.2 + 0.67 = 2.665 here. Propagation delay is 3.3356 ps per millimetre multiplied by the square root of the effective permittivity, so 3.3356 × 1.6325 = 5.446 ps/mm, or 138.3 ps per inch. Stripline has no air above it, so its effective permittivity is the full laminate value and it is correspondingly slower — about 174 ps per inch on the same material, which is a real timing difference when a bus is routed partly on outer and partly on inner layers.
The differential estimate uses the widely published coupling correction Zdiff = 2Z₀(1 − 0.48 e−0.96s/h) for microstrip. At s = 0.25 mm over h = 0.15 mm the ratio is 1.667, the exponential is 0.202, and the correction factor is 0.903, giving 2 × 49.2 × 0.903 = 88.9 Ω. Widen the spacing and the figure climbs toward the uncoupled limit of twice the single-ended value.
Why a Formula Cannot Confirm a Controlled-Impedance Board
The equations above model a rectangular trace of uniform width over a perfectly flat, perfectly homogeneous dielectric of exactly known permittivity. A real board is none of those things, and each departure moves the answer.
Etching produces a trapezoidal cross-section, not a rectangle, typically with the top narrower than the bottom by an angle-dependent amount. Prepreg thickness after lamination depends on how much resin flowed into the copper-free areas nearby, so the same prepreg finishes thinner under a dense copper region than under a sparse one. The dielectric constant depends on the local resin-to-glass ratio, so a trace running over a glass bundle sees a different permittivity from one running over resin in the weave opening — the origin of fibre weave skew in high-speed differential pairs. Solder mask over a microstrip lowers its impedance by a couple of ohms, and none of these equations include it.
The consequence is that closed-form results routinely land several ohms from the measured value, and a typical controlled-impedance specification is ten per cent, which on a 50-ohm line is only five ohms of total budget. Serious controlled-impedance work therefore runs a two-dimensional field solver against the fabricator's actual stack-up, then verifies with a TDR measurement on a test coupon manufactured on the same panel as the boards. IPC, publishing as the Global Electronics Association, maintains both the design guidance and the test-method documents that describe how that coupon measurement is performed.
Which Variable Actually Moves the Answer
Dielectric height is the strongest single lever. Impedance depends on it inside a logarithm, but the range available is wide: doubling the height from 0.1 mm to 0.2 mm raises impedance by roughly fifteen ohms on a typical geometry. That is why the stack-up is the first thing to fix and the artwork second.
Trace width is next and is the variable the fabricator will tune, since it is the only one they can change without altering the material set. It works in the opposite direction: wider is lower impedance. Dielectric constant matters less than people expect for impedance because it appears under a square root, but it matters a great deal for propagation delay, which is where a low-loss laminate earns its cost on a long link.
Copper thickness is a small effect on impedance and a large one on manufacturability. Going from half-ounce to two-ounce copper drops a 50-ohm microstrip by only a couple of ohms, but it changes the achievable minimum width and spacing substantially. The crosstalk calculator covers what happens when two of these lines run beside each other, and the attenuation calculator handles the loss that accumulates along a long line rather than the impedance of a short one.
Where Impedance Control Stops Mattering
Not every trace needs to be a transmission line, and treating every net as one wastes board area. The usual criterion compares the electrical length of the trace to the signal's edge rate. If the round-trip delay along the trace is much shorter than the rise time — a common rule of thumb is less than about one-sixth of it — reflections settle within the edge itself and the trace behaves as a lumped connection.
At 138 ps per inch, a two-inch microstrip has a one-way delay of 276 ps and a round trip of about 550 ps. A driver with a 2 ns edge will not notice it. A driver with a 200 ps edge very much will, and that driver's edge rate is set by the silicon process, not by the clock frequency on your schematic. This is why a slow bus built from a modern part still needs transmission line discipline. The underlying guided-wave theory is developed in MIT OpenCourseWare's 6.013 Electromagnetics and Applications course, which derives the impedance and propagation relations these fits approximate.
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Browse All Free Tools Talk to Arb DigitalCommon Mistakes to Avoid
- Using total board thickness as the dielectric height — microstrip height is the distance to the nearest solid reference plane, which on a six-layer board is usually a small fraction of the stack.
- Assuming FR-4 has one dielectric constant — it is a material class with values from roughly 3.8 to 4.7 that also fall with frequency, and picking the wrong end shifts impedance by several ohms.
- Forgetting solder mask over a microstrip — it typically lowers impedance by one to three ohms, and none of the closed-form equations account for it.
- Running the equations outside their fitted window — the microstrip fit is valid for a width-to-height ratio of roughly 0.1 to 3.0, and results outside that should not be trusted.
- Treating a calculated impedance as a verified one — controlled impedance is confirmed by the fabricator's stack-up and a TDR measurement on a coupon, never by a formula.
Related Free Tools From Arb Digital
For the current-carrying and thermal side of trace sizing, the PCB trace width calculator applies IPC-2221 and answers a completely different question from this page. The crosstalk calculator takes the same geometry and estimates coupling to a neighbour, and the impedance matching calculator covers what to do when a source and load impedance do not agree. For components rather than traces, the RLC impedance calculator, the reactance calculator and the capacitance calculator handle terminations and decoupling. The cable impedance calculator does the equivalent job for coax and twisted pair, and the wavelength calculator sets stub and via-stitching intervals. Everything is on the free online tools hub.
Frequently Asked Questions
The closed-form microstrip and stripline equations published in IPC-2141, the design guide for controlled impedance boards issued by IPC, now trading as the Global Electronics Association. They are empirical fits to field-solver results rather than derivations, which is why they contain unexplained numeric constants and carry a stated range of validity.
Use it to choose a starting geometry and to understand which variable moves the answer. A real board is confirmed by the fabricator's stack-up, ideally modelled in a two-dimensional field solver, and verified by a time-domain reflectometry measurement on a test coupon built on the same panel. A closed-form formula cannot account for etch taper, resin flow or glass weave.
They answer unrelated questions. This page computes characteristic impedance from geometry, which is a signal integrity problem governed by IPC-2141. The trace width calculator sizes copper to carry current without excessive temperature rise, which is a thermal problem governed by IPC-2221. Both constraints apply to a real trace and the harder one wins.
Because propagation delay depends on the effective permittivity the wave experiences, and a stripline is surrounded entirely by laminate while a microstrip has air above it. The microstrip's effective permittivity is therefore well below the laminate value and the wave travels faster. On typical FR-4 the difference is roughly 138 against 174 picoseconds per inch.
They typically land within a few ohms of a field solver inside their validity window, which sounds close until you notice that a ten per cent tolerance on a 50-ohm line is only five ohms of total budget. Etch taper, solder mask, resin flow variation and glass weave all move the real value and none of them appear in the equations.
Yes, on microstrip. Adding dielectric above a trace that previously had air there raises the effective permittivity and lowers the impedance, typically by one to three ohms depending on mask thickness and coverage. Stripline is unaffected because it is already buried. None of the closed-form equations model it.
When the round-trip propagation delay along it is a significant fraction of the driver's rise time, commonly taken as more than about one-sixth. That threshold depends on the edge rate of the silicon, not on the clock frequency, so a slow bus driven by a modern fast-edged part still needs transmission line treatment.
This tool is provided for educational and preliminary design use. It applies published empirical approximations to idealised geometry and models no etch taper, solder mask, resin flow, glass weave, plating variation or dielectric loss. Controlled impedance must be established with the fabricator's stack-up and verified by measurement.
